Affiliated to FMCAD'19
October 22 - 25, 2019
This is the 10th competitive event for hardware model checkers.
This year our focus is on introducing a word-level track based on the BTOR2 format, which is described in our CAV'18 paper. The Btor2Tools tool suite provides a generic parser Btor2Parser and a simulator BtorSIM, which are useful for parsing and random simulation of BTOR2 models, as well as for witness checking. There is also a simple bounded model checker BtorMC, distributed as part of Boolector.
Since this year will be the first time with an experimental word-level track there will be no declared winners.
The hardware setup is identical to the last competition. It is running on our Ubuntu 18.04.3 LTS 64 bit cluster with two Intel(R) Xeon(R) CPU E5-2620 v4 @ 2.10GHz CPUs and 128 GB of main memory on each node.
Each solver has full access to both processors on one node, thus combined 16 cores (32 virtual cores) and 128 GB of main memory. Accordingly a memory limit of 120GB will be enforced. As in the previous competition in 2017 we will further use a time limit of 1 hour of wall clock-time.
Registration and first versions of model checkers are due on September 28.
It is possible to send updates of model checkers until October 13.
New benchmarks are accepted untli October 13 as well.
All submission dates are anywhere on earth.
HWMCC'19 is organized by
HWMCC'17 at FMCAD'17,