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Dr. Daniela Kaufmann
From July 2016 until April 2020, I was a Ph.D. student of
Computer Science at JKU, supervised
by Prof. Armin Biere.
My thesis is on Formal
Verification of Multiplier Circuits using Computer Algebra.
A list of my publications can be found here: Publications
- Arithmetic Circuit Verification
- Computer Algebra
- Algebraic Proof Systems
- Rigorous Systems Engineering
Note: some of them are published under my maiden name 'Ritirc'.
for Multiplier Verification , CASC 2020, (online).
Verification of Multiplier Circuits using Computer Algebra ,
PhD Defense 2020, Johannes Kepler University, Linz, Austria.
- From DRUP to
PAC and Back , DATE 2020 (online), Grenoble, France.
SAT and Computer Algebra to Successfully Verify Large Multiplier
Circuits , PLunch Talk 2019, Carnegie Mellon University,
Pittsburgh, PA, USA.
SAT and Computer Algebra to successfully verify Large Multiplier
Circuits , BARC Talk 2019, University of Copenhagen,
Large Multipliers by Combining SAT and Computer Algebra , FMCAD
19, San Jose, CA, USA.
Practical Polynomial Calculus for Arithmetic Circuit
Verification , SC-2 Workshop at FLoC 2018 , Oxford, United
- On the
Problem of Arithmetic Circuit Verification Using Computer
Algebra, Theory Reading Group Meeting 2018, KTH Royal Institute
of Technology, Stockholm, Sweden.
Verification of Multipliers Using Computer Algebra, FMCAD 2017,
- Complexity of
Circuit Ideal Membership Testing, SC-2 Workshop 2017,
Science Park 3 (SCP3), 2nd
Room S3 0254
+43 732 2468 4549 (phone)
Institute for Formal Models and Verification
Johannes Kepler University