FMCAD 2009
Formal Methods in Computer Aided Design
Austin, Texas, USA
November 15 - 18

Wednesday Keynote, 18. November, 09:00 - 10:00

Post Silicon Validation/Verification practices in the PC industry

John D. Barton, Intel


John will give an overview of Intel Corporation's post silicon validation approach. He will focus on the unique advantages a post silicon approach offers over simulation and emulation based approaches. He will survey the major gaps in fundamental knowledge and tools suggesting potential research or product opportunities.


John D. Barton is vice president, Digital Enterprise Group, and general manager, Platform Validation Engineering. He is responsible for an organization that performs post-silicon validation/verification for Intel platforms.

Barton's responsibilities include the verification of logically correct operation of microprocessors and chipsets, verification of platform electrical interconnects, software compatibility and security. Barton’s organization also works directly with customers and third parties to ensure key products and technologies ramp with high quality.

Barton joined Intel in 1982 as a software engineer in the Development Systems Operation. He later managed various hardware and software tools for Intel's X86 and 80960 processor families. Barton subsequently managed customer support for Intel's Supercomputer Systems Operation before joining the Intel® Pentium®Pro team as validation manager.

Barton graduated from Oregon State University in 1980 with a bachelor's degree in computer science.