Hardware Verification Workshop 2010

First International Workshop

July 15, Edinburgh, United Kingdom
affiliated with CAV'10 at next FLOC'10

[ cfp | invited talks | overview | dates ]

News

The official Call for Papers is available also in ASCII.

Invited Talks

Cindy Eisner
IBM, Israel

Sharad Malik
Princeton University, USA

Overview

When model checking was first conceived it was a purely academic notion with no practical use. Through a series of breakthrough developments model checking, and formal verification in general, have become extensively used and relied upon in the semiconductor industry. However, the problem is far from being solved. In fact, the rate at which verification capabilities increase does not match the rate at which design complexity and size grow. This phenomenon is called the "verification gap", and it is one of the biggest concerns of the industry. Recently, however, we see a steady dwindling in the number of publications that specifically target hardware.

The purpose of this workshop is to rekindle some of the interest and enthusiasm towards hardware verification. Through this workshop we would like to encourage new and daring directions, to provide a stage for ideas in early developmental stages, and initiate discussions that define the challenges that remain to be tackled with.

The scope of the workshop will include both general research in formal verification techniques of hardware designs as well as specific issues related to the development of model checking tools. In addition, we will integrate the Hardware Model Checking Competition into the agenda of the workshop, which will further raise the level of interest in the workshop. Combining the competition with the workshop will help us attract papers that are related to the competing tools and make the event more complete in scope.

For more details on the competition and on the submission process for papers, benchmarks and model checkers, see the Call for Papers.